1. Field of the Invention
The present invention relates to a context-based adaptive binary arithmetic decoding method and apparatus, and more particularly, to a method and apparatus for implementing in hardware context-based adaptive arithmetic decoding as one of entropy coding techniques in an image decoding apparatus.
2. Description of the Related Art
Arithmetic coding is known as one of most effective entropy coding technologies. However, since the arithmetic coding has high complexity and requires complicated hardware, it has not been used for image compression. However, recently, a H.264/MPEG4 pt. 10 AVC codec developed by Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG adapts the arithmetic coding to enhance coding efficiency (see “Text of ISO/IEC FDIS 14496-10: Information Technology-Coding of audio-visual objects—Part 10: Advanced Video Coding”, ISO/IEC JTC 1/SC 29/WG 11, N5555, March, 2003). An arithmetic decoder for implementing the arithmetic coding based on the H.264/MPEG4 pt. 10 AVC codec is a context-based adaptive binary arithmetic decoder (for example, H.264/MPEG4 pt. 10 AVC decoder). The H.264/MPEG4 pt. 10 AVC decoder predicts probability values according to contexts and performs arithmetic decoding using a QM coder, in the same manner as that used in a conventional JBIG (see “Text of ITU-T Recommendation T. 82 (1993)|ISO/IEC 11544: Information technology—Coded representation of picture and audio information-Progressive bi-level image compression”).
FIG. 1 is a block diagram schematically showing an encoder (H.264/AVC encoder) for H.264/AVC context-based adaptive binary arithmetic encoding.
Referring to FIG. 1, a binarization unit 120 binarizes an input value according to a syntax signal received from a syntax unit 110, thus creating a binary value. Here, the syntax signal may be a motion vector flag, a block mode flag, a residue flag, etc. The motion vector flag, the block mode flag, and the residue flag are classified according to the types of signals to be decoded by the syntax signal. That is, if a motion vector flag is input to the binarization unit 120, a motion vector value is decoded, if a block mode flag is input to the binarization unit 120, a block mode value is decoded, and if a residue flag is input to the binarization unit 120, a residue value is decoded.
Here, a value input to the binarization unit 120 is a signal sampled and quantized from an image signal. A context unit 140 receives a model signal for initializing a context from a model unit 130, receives the syntax signal from the syntax unit 110, selects a corresponding context, and then outputs the selected context to the QM coder 150. The QM coder 150 performs arithmetic encoding on a value received from the binarization unit 120 on the basis of the context received from the context unit 140. Each context contains a state value to encode a corresponding binarization value. The QM coder 150 loads the state value and reads a probability value corresponding to the state value from a table, thus performing arithmetic encoding. A bit stream subjected to the arithmetic encoding by the QM coder 150 is transmitted to a decoder.
FIG. 2 is a block diagram schematically showing a decoder (H.264/AVC decoder) for H.264/AVC context-based adaptive binary arithmetic decoding.
Referring to FIG. 2, a context unit 210 receives the model signal (initial model signal) through the bit stream received from the H.254/AVC encoder and receives a syntax information signal from the syntax unit 230, thus extracting a context according to the syntax signal. A QM coder 220 performs arithmetic decoding on the bit stream received from the encoder on the basis of the context extracted by the context unit 210. An inverse binarization unit 240 receives the syntax information signal from the syntax unit 230 and inverse-binarizes a binary value output from the QM coder 220 on the basis of the syntax information signal, thus creating and outputing a value. The value output from the inverse binarization unit 240 is subjected to inverse-quantization and inverse-transform and then output as an original image signal. The QM coder 220 is a specific QM coder suitable for the H.264/AVC decoder.
FIG. 3 is a block diagram provided for explaining in detail the operation of the context unit 210 and the QM coder 220 of FIG. 2.
The configuration of FIG. 3, which includes a context unit 310, a general mode arithmetic decoder 320, and a bypass mode arithmetic decoder 330, is aimed to reduce complexity of arithmetic decoding.
The context unit 310, which is a device suitable for use in a context-based technique, extracts different contexts according to the states of adjacent symbols so that probability values can be adaptively obtained when given symbols are decoded, thereby increasing compression efficiency. A context extracted from the context unit 310 uses the number of pre-decoded specific residues. An extracted context consists of two factors of a state value and a MPS (Most Probable Symbol), which represent information regarding probability characteristic. The context unit 310 storing a plurality of contexts extracts a corresponding context and outputs it to the general mode arithmetic decoder 320.
The general mode arithmetic decoder 320 performs arithmetic decoding on the basis of a context output from the context unit 310. A decoder (H.264/MPEG-4 pt. 10 AVC decoder) based on the H.264/MPEG-4 pt. 10 AVC codec performs both general mode arithmetic decoding and bypass mode arithmetic decoding. For that, the bypass mode arithmetic decoder 330 is newly provided in addition to the general mode arithmetic decoder 320 having the same configuration as the conventional QM coder, differently from the conventional arithmetic decoder. In the H.264/MPEG-4 pt. 10 AVC decoder, in order to reduce complexity, a 4×64 table in which probability values for a LPS (Least Probable Symbol) are quantized, is used. The 4×64 table will be described in detail later.
Meanwhile, if a probability value for a MPS is equal to that for a LPS, decoding by the general mode arithmetic decoder 320 is impossible. In this case, the bypass mode arithmetic decoder 330 is used. A bypass mode performed by the bypass mode arithmetic decoder 330 is applied when a probability value for a MPS is equal to that for a LPS and when a residue value is larger than 13. When a residue value is larger than 13, the general mode arithmetic decoder 320 controls a switch 340 to operate the bypass mode arithmetic decoder 330. In detail, the general mode arithmetic decoder 330 counts the number of symbols to be decoded, determines whether a residue value is larger than 13, and controls the switch 340 to operate the bypass mode arithmetic decoder 330 if the residue value is larger than 13.
Since the H.264/MPEG-4 pt. 10 AVC decoder described above maps a symbol to a binary value and decodes the binary value, many operations must be performed to obtain a symbol value. For example, assume that a binary value corresponding to a residue value 4 is ‘11110’. In this case, in the conventional arithmetic decoder, since one probability value is given to the residue value 4, one decoding operation is performed to obtain a result value. However, in the H.264/MPEG-4 pt. 10 AVC decoder, since respective figures of the binary value ‘11110’ are decoded, five arithmetic decoding operations must be performed to obtain a residue value 4. The H.264/MPEG-4 pt. 10 AVC decoder performs no muliplication when decoding the binary value, thereby reducing complexity. However, since the H.264/MPEG-4 pt. 10 AVC decoder performs decoding operations in units of bits, it can not efficiently reduce operation complexity.
Also, the H.264/MPEG-4 pt. 10 AVC decoder has a similar basic algorithm with the conventional JBIG QM coder. However, in the H.264/MPEG-4 pt. 10 AVC decoder, many corrections and complements have been applied on a process of excluding multiplication for reducing complexity, compared with the conventional JBIG QM coder. Primarily, the H.264/MPEG-4 pt. 10 AVC decoder decides a context using the number of previously decoded specific residue values instead of information for adjacent blocks. Secondarily, the H.264/MPEG-4 pt. 10 AVC decoder has two modes of a general mode and a bypass mode. The H.264/MPEG-4 pt. 10 AVC decoder quantizes predicted probability values in order to reduce complexity when probability values are predicted, differently from the conventional arithmetic decoder (for example, JBIG QM coder). However, it is still difficult to hardwarily implement a H.264/MPEG-4 pt. 10 AVC decoder having both a general mode and a bypass mode, using an existing hardware.